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www.irf.com 1 hexfet ? power mosfet v dss = 100v r ds(on) = 26.5m i d = 36a this hexfet ? power mosfet utilizes the latest processing techniques to achieve extremely lowon-resistance per silicon area. additional features of this design are a 175c junction operating temperature, fast switching speed and improved repetitive avalanche rating.these features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. s d g description features irf540zpbf irf540zspbf IRF540ZLPBF d 2 pak irf540zspbf to-220ab irf540zpbf to-262 IRF540ZLPBF absolute maximum ratings parameter units i d @ t c = 25c continuous drain current, v gs @ 10v (silicon limited) i d @ t c = 100c continuous drain current, v gs @ 10v a i dm p u l se d d ra i n c urrent p d @t c = 25c power dissipation w linear derating factor w/c v gs gate-to-source voltage v e as (thermally limited) si n gl e p u l se a va l anc h e e ner gy mj e as (tested ) si n gl e p u l se a va l anc h e e ner gy t este d v a l ue i ar a va l anc h e c urrent a e ar r epet i t i ve a va l anc h e e ner gy mj t j operating junction and t stg storage temperature range c soldering temperature, for 10 seconds mounting torque, 6-32 or m3 screw thermal resistance parameter typ. max. units r jc junction-to-case CCC 1.64 c/w r cs case-to-sink, flat greased surface 0.50 CCC r ja junction-to-ambient CCC 62 r ja junction-to-ambient (pcb mount) CCC 40 -55 to + 175 300 (1.6mm from case ) 10 lbf in (1.1n m) 92 0.61 20 max. 3625 140 120 83 see fig.12a, 12b, 15, 16 advanced process technology ultra low on-resistance 175c operating temperature fast switching repetitive avalanche allowed up to tjmax lead-free pd - 95531a downloaded from: http:///

2 www.irf.com s d g electrical characteristics @ t j = 25c (unless otherwise specified) parameter min. typ. max. units v (br)dss drain-to-source breakdown voltage 100 CCC CCC v ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.093 CCC v/c r ds(on) static drain-to-source on-resistance CCC 21 26.5 m v gs(th) gate threshold voltage 2.0 CCC 4.0 v gfs forward transconductance 36 CCC CCC v i dss drain-to-source leakage current CCC CCC 20 a CCC CCC 250 i gss gate-to-source forward leakage CCC CCC 200 na gate-to-source reverse leakage CCC CCC -200 q g total gate charge CCC 42 63 q gs gate-to-source charge CCC 9.7 CCC nc q gd gate-to-drain ("miller") charge CCC 15 CCC t d(on) turn-on delay time CCC 15 CCC t r rise time CCC 51 CCC t d(off) turn-off delay time CCC 43 CCC ns t f fall time CCC 39 CCC l d internal drain inductance CCC 4.5 CCC between lead, nh 6mm (0.25in.) l s internal source inductance CCC 7.5 CCC from package and center of die contact c iss input capacitance CCC 1770 CCC c oss output capacitance CCC 180 CCC c rss reverse transfer capacitance CCC 100 CCC pf c oss output capacitance CCC 730 CCC c oss output capacitance CCC 110 CCC c oss eff. effective output capacitance CCC 170 CCC source-drain ratin g s and characteristics parameter min. typ. max. units i s continuous source current CCC CCC 36 (body diode) a i sm pulsed source current CCC CCC 140 (body diode) v sd diode forward voltage CCC CCC 1.3 v t rr reverse recovery time CCC 33 50 ns q rr reverse recovery charge CCC 41 62 nc t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) v gs = 0v, v ds = 1.0v, ? = 1.0mhz v gs = 0v, v ds = 80v, ? = 1.0mhz v gs = 0v, v ds = 0v to 80v v gs = 10v v dd = 50v i d = 22a r g = 12 t j = 25c, i s = 22a, v gs = 0v t j = 25c, i f = 22a, v dd = 50v di/dt = 100a/s conditions v gs = 0v, i d = 250a reference to 25c, i d = 1ma v gs = 10v, i d = 22a v ds = v gs , i d = 250a v ds = 100v, v gs = 0v v ds = 100v, v gs = 0v, t j = 125c mosfet symbol showing the integral reverse p-n junction diode. v ds = 25v, i d = 22a i d = 22a v ds = 80v conditions v gs = 10v v gs = 0v v ds = 25v ? = 1.0mhz v gs = 20v v gs = -20v downloaded from: http:///

www.irf.com 3 fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. typical forward transconductance vs. drain current 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 25c 4.5v vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.5v 0 1 10 100 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 60s pulse width tj = 175c 4.5v vgs top 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v bottom 4.5v 4.0 5.0 6.0 7.0 v gs , gate-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) v ds = 25v 60s pulse width t j = 25c t j = 175c 0 1 02 03 04 05 0 i d, drain-to-source current (a) 0 20 40 60 80 g f s , f o r w a r d t r a n s c o n d u c t a n c e ( s ) t j = 25c t j = 175c v ds = 10v 380s pulse width downloaded from: http:///

4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 1 10 100 v ds , drain-to-source voltage (v) 0 500 1000 1500 2000 2500 3000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 1 02 03 04 05 06 0 q g total gate charge (nc) 0 4 8 12 16 20 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 80v vds= 50v vds= 20v i d = 22a for test circuit see figure 13 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v sd , source-todrain voltage (v) 0.1 1.0 10.0 100.0 1000.0 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v 1 10 100 1000 v ds , drain-tosource voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec downloaded from: http:///

www.irf.com 5 fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature fig 10. normalized on-resistance vs. temperature 25 50 75 100 125 150 175 t j , junction temperature (c) 0 10 20 30 40 i d , d r a i n c u r r e n t ( a ) -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 2.5 3.0 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 22a v gs = 10v 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 10 t h e r m a l r e s p o n s e ( z t h j c ) 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) downloaded from: http:///

6 www.irf.com q g q gs q gd v g charge fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as fig 14. threshold voltage vs. temperature r g i as 0.01 t p d.u.t l v ds + - v dd driver a 15v 20v v gs -75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 1.5 2.0 2.5 3.0 3.5 4.0 v g s ( t h ) g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a 1k vcc dut 0 l 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 20 40 60 80 100 120 140 160 180 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 8.3a 14a bottom 20a downloaded from: http:///

www.irf.com 7 fig 15. typical avalanche current vs.pulsewidth fig 16. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 15, 16:(for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far in excess of t jmax . this is validated for every part type.2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 12a, 12b. 4. p d (ave) = average power dissipation per single avalanche pulse.5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 15, 16). t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figure 11) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 1.0e-08 1.0e-07 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 0.1 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav assuming ? tj = 25c due to avalanche losses 0.01 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 10 20 30 40 50 60 70 80 90 100 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 10% duty cycle i d = 20a downloaded from: http:///

8 www.irf.com fig 17.

for n-channel hexfet power mosfets
?
? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period
+ - + + + - - - ?
?
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# $$ ? !"!!%" v ds 90%10% v gs t d(on) t r t d(off) t f &' 1 (
# 0.1 % + - fig 18a. switching time test circuit fig 18b. switching time waveforms downloaded from: http:///

www.irf.com 9 to-220ab package is not recommended for surface mount application

int ernat ional part number rectifier lot code assembly logo year 0 = 2000 dat e code week 19 line c lot code 1789 example: t his is an irf 1010 note: "p" in assembly line position i ndi cates "l ead - f r ee" in the assembly line "c" as s embled on ww 19, 2000 notes: 1. for an automotive qualified version of this part please see http://www.irf.com/product-info/auto/ 2. for the most current drawing please refer to ir website at http://www.irf.com/package/ downloaded from: http:///

10 www.irf.com

dat e code year 0 = 2000 we e k 02 a = as s e mb l y s it e code re ct if ie r int e rnat ional part number p = designates lead - free product (optional) f530s in t he ass embly line "l" as s e mb l e d on ww 02, 2000 t his is an irf 530s wit h lot code 8024 int ernat ional logo re ct if ie r lot code as s e mb l y year 0 = 2000 part number dat e code line l week 02 or f530s logo as s e mb l y lot code notes: 1. for an automotive qualified version of this part please see http://www.irf.com/product-info/auto/ 2. for the most current drawing please refer to ir website at http://www.irf.com/package/ downloaded from: http:///

www.irf.com 11 assembly lot code rect if ier int ernational as s e mb l e d on ww 19, 1997 note: "p" in as s embly line pos ition indicates "l ead-f ree" in the assembly line "c" logo this is an irl3103l lot code 1789 example: line c dat e code we e k 19 year 7 = 1997 part numbe r part number logo lot code assembly int ernational rect if ier product (optional) p = designat es lead-free a = as s e mb l y s it e code we e k 19 year 7 = 1997 dat e code or notes: 1. for an automotive qualified version of this part please see http://www.irf.com/product-info/auto/ 2. for the most current drawing please refer to ir website at http://www.irf.com/package/ to-262 package outlinedimensions are shown in millimeters (inches) downloaded from: http:///

12 www.irf.com data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 07/2010 to-220ab package is not recommended for surface mount application. repetitive rating; pulse width limited by max. junction temperature. (see fig. 11). limited by t jmax , starting t j = 25c, l = 0.46mh r g = 25 , i as = 20a, v gs =10v. part not recommended for use above this value. pulse width 1.0ms; duty cycle 2%. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss .
limited by t jmax , see fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. this value determined from sample failure population. 100% tested to this value in production. this is only applied to to-220ab pakcage. this is applied to d 2 pak, when mounted on 1" square pcb (fr- 4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. 3 4 4 trr feed direction 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) trl feed direction 10.90 (.429) 10.70 (.421) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 4.72 (.136) 4.52 (.178) 24.30 (.957) 23.90 (.941) 0.368 (.0145) 0.342 (.0135) 1.60 (.063) 1.50 (.059) 13.50 (.532) 12.80 (.504) 330.00 (14.173) max. 27.40 (1.079) 23.90 (.941) 60.00 (2.362) min. 30.40 (1.197) max. 26.40 (1.039) 24.40 (.961) notes : 1. comforms to eia-418. 2. controlling dimension: millimeter. 3. dimension measured @ hub. 4. includes flange distortion @ outer edge. d 2 pak tape & reel infomation downloaded from: http:///

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